library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity fsmd_filter is
port ( clk, reset, start: in std_logic; 
	data: in unsigned(7 downto 0);  
	wfiltered: out unsigned(7 downto 0);  
	error: out signed(7 downto 0) ); 
end entity fsmd_filter; 

use work.mypackage.all; 
architecture FSMD of fsmd_filter is  
	type state is (idle1,idle2,op);  
	signal state_ps, state_ns: state; 
	signal r1_ps,r1_ns,r2_ps,r2_ns: 
	unsigned(7 downto 0); 
	begin 
	p1:process(clk,reset)  
	begin  
	if reset='1' then 
	state_ps <= idle1;  
	r1_ps <= (others => '0') ;  
	r2_ps <= (others => '0') ;  
	elsif (clk'event and clk='1') then  
	state_ps <= state_ns;  
	r1_ps <= r1_ns ;  
	r2_ps <= r2_ns ;  
	end if; 
	end process p1; 
	
	p2:process(state_ps,r1_ps,r2_ps) is  
	variable f_tmp:unsigned(15 downto 0); 
	begin  
	case state_ps is  
	when idle1 =>  
		wfiltered<=(others => '0') ;  
		error<=(others => '0') ;  
		r1_ns <= data;  
		r2_ns <= (others => '0') ;   
		state_ns <=idle2;  
	when idle2 =>  
		wfiltered<=(others => '0') ;  
		error<=(others => '0') ;  
		r1_ns <= r1_ps;  
		r2_ns <= data;  
		if start='1' then  
			state_ns <= op;  
		else  
			state_ns <= idle1;  
		end if;  
	when op =>  
		f_tmp:=ffilter(r2_ps,r1_ps);  
		wfiltered<= f_tmp(15 downto 8); 
		error<= signed(f_tmp(7 downto 0));  
		r1_ns<=r2_ps;  
		r2_ns<=data;
		state_ns <= op;  
		end case; 
		end process; 
end architecture FSMD; 